Plenary Lecture

Design Challenges and Opportunities of the “End of Scaling” Nanoscale CMOS

Prof. Ching-Te Chuang
IBM T. J. Watson Research Center
Yorktown Heights, NY 10598, U. S. A.
e-mail: ctchuang@us.ibm.com

Abstract: This presentation reviews the challenges and opportunities of high-performance digital design in the “End of Scaling” nanoscale CMOS technologies. The device structure evolution, material enhancement, and major design challenges are discussed. Examples of logic circuit and SRAM design techniques to overcome the challenges and to mitigate various performance/reliability constraints in conventional planar CMOS technology are given. Scaled/emerging technologies such as scaled PD/SOI, UT/SOI, strained-Si channel device, hybrid orientation technology, and multi-gate FinFET are addressed with particular emphases on the implications and impacts on circuit design. Finally, novel logic circuit, SRAM, and power-gating schemes exploiting unique structures and properties of emerging devices are discussed.

Brief Biography of the Speaker:
Ching-Te Chuang received the B.S.E.E. from National Taiwan University, Taipei, Taiwan in 1975 and Ph.D. degree in Electrical Engineering from University of California, Berkeley, CA in 1982.
From 1977 to 1982 he was a research assistant in the Electronics Research Laboratory, University of California, Berkeley, working on bulk and surface acoustic wave devices. He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY in 1982, working on scaled bipolar devices, technology, and circuits. From 1986 to 1988, he was Manager of the Bipolar VLSI Design Group, working on low-power bipolar circuits, high-speed high-density bipolar SRAMs, multi-Gb/s fiber-optic data-link circuits, and scaling issues for bipolar/BiCMOS devices and circuits. Since 1988, he has managed the High Performance Circuit Group, investigating high-performance logic and memory circuits. Since 1993, his group has been primarily responsible for the circuit design of IBM’s high-performance CMOS microprocessors for enterprise servers, PowerPC workstations, and game/media processors. Since 1996, he has been leading the efforts in evaluating and exploring scaled/emerging technologies, such as PD/SOI, UT/SOI, strained-Si devices, hybrid orientation technology, and multi-gate/FinFET devices, for high-performance logic and SRAM applications.
Dr. Chuang served on the Device Technology Program Committee for IEDM in 1986 and 1987, and the Program Committee for Symposium on VLSI Circuits from 1992 to 2006. He was the Publication/Publicity Chairman for Symposium on VLSI Technology and Symposium on VLSI Circuits in 1993 and 1994, and the Best Student Paper Award Sub-Committee Chairman for Symposium on VLSI Circuits from 2004 to 2006. He was elected an IEEE Fellow in 1994 “For contributions to high-performance bipolar devices, circuits, and technology". He has authored many invited papers in international journals such as International J. of High Speed Electronics, Proceedings of IEEE, and IEEE Circuits and Devices Magazine. He has presented numerous plenary, invited or tutorial papers/talks at international conferences such as International SOI Conf., DAC, VLSI-TSA, ISSCC Microprocessor Design Workshop, VLSI Circuit Symposium Short Course, ISQED, ICCAD, APMC, VLSI-DAT, and ISCAS, etc. He was the co-recipient of the Best Paper Award at the 2000 IEEE International SOI Conference. He holds 19 U.S. patents with another 17 pending. He has authored or coauthored over 240 papers.